pmc: SQ_WAIT_INST_ANY SQ_WAVES SQ_WAVES_RESTORED SQ_WAVES_SAVED SQ_WAVE_CYCLES TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum TCP_UTCL1_TRANSLATION_MISS_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCC_EA0_WRREQ_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_HIT[0] TCC_HIT[100] TCC_HIT[101] TCC_HIT[102] TCC_HIT[103] TCC_HIT[104] TCC_HIT[105] TCC_HIT[106] TCC_HIT[107] TCC_HIT[108] TCC_HIT[109] TCC_HIT[10] TCC_HIT[110] TCC_HIT[111] TCC_HIT[112] TCC_HIT[113] TCC_HIT[114] TCC_HIT[115] TCC_HIT[116] TCC_HIT[117] TCC_HIT[118] TCC_HIT[119] TCC_HIT[11] TCC_HIT[120] TCC_HIT[121] TCC_HIT[122] TCC_HIT[123] TCC_HIT[124] TCC_HIT[125] TCC_HIT[126] TCC_HIT[127] TCC_HIT[12] TCC_HIT[13] TCC_HIT[14] TCC_HIT[15] TCC_HIT[16] TCC_HIT[17] TCC_HIT[18] TCC_HIT[19] TCC_HIT[1] TCC_HIT[20] TCC_HIT[21] TCC_HIT[22] TCC_HIT[23] TCC_HIT[24] TCC_HIT[25] TCC_HIT[26] TCC_HIT[27] TCC_HIT[28] TCC_HIT[29] TCC_HIT[2] TCC_HIT[30] TCC_HIT[31] TCC_HIT[32] TCC_HIT[33] TCC_HIT[34] TCC_HIT[35] TCC_HIT[36] TCC_HIT[37] TCC_HIT[38] TCC_HIT[39] TCC_HIT[3] TCC_HIT[40] TCC_HIT[41] TCC_HIT[42] TCC_HIT[43] TCC_HIT[44] TCC_HIT[45] TCC_HIT[46] TCC_HIT[47] TCC_HIT[48] TCC_HIT[49] TCC_HIT[4] TCC_HIT[50] TCC_HIT[51] TCC_HIT[52] TCC_HIT[53] TCC_HIT[54] TCC_HIT[55] TCC_HIT[56] TCC_HIT[57] TCC_HIT[58] TCC_HIT[59] TCC_HIT[5] TCC_HIT[60] TCC_HIT[61] TCC_HIT[62] TCC_HIT[63] TCC_HIT[64] TCC_HIT[65] TCC_HIT[66] TCC_HIT[67] TCC_HIT[68] TCC_HIT[69] TCC_HIT[6] TCC_HIT[70] TCC_HIT[71] TCC_HIT[72] TCC_HIT[73] TCC_HIT[74] TCC_HIT[75] TCC_HIT[76] TCC_HIT[77] TCC_HIT[78] TCC_HIT[79] TCC_HIT[7] TCC_HIT[80] TCC_HIT[81] TCC_HIT[82] TCC_HIT[83] TCC_HIT[84] TCC_HIT[85] TCC_HIT[86] TCC_HIT[87] TCC_HIT[88] TCC_HIT[89] TCC_HIT[8] TCC_HIT[90] TCC_HIT[91] TCC_HIT[92] TCC_HIT[93] TCC_HIT[94] TCC_HIT[95] TCC_HIT[96] TCC_HIT[97] TCC_HIT[98] TCC_HIT[99] TCC_HIT[9] TCC_HIT_sum

gpu:
range:
kernel:
